The present invention relates to a technique for a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device having elements driven by different supply voltages on the same semiconductor substrate.
For example, Japanese Patent Laid-Open No. 5-120882 discloses the technique in which the voltage level of one or both of a memory cell power-supply line and a word line is boosted to achieve a low-voltage operation of an SRAM (Static Random Access Memory). In this SRAM, MOS•FETs (Metal Oxide Semiconductor Field Effect Transistors) driven by different supply voltages are mixed on the same semiconductor substrate, and different well bias voltages are supplied to each of the MOSFETs driven by different supply voltages.
Also, for example, Japanese Patent Laid-Open No. 11-7776 discloses the method of supplying level-up voltage to a memory cell, in which the voltage (VDD) before the boosting is supplied as n well bias voltage of a p channel MOS•FET.
Additionally, for example, Japanese Patent Laid-Open No. 5-267617 discloses the structure in which the memory cell of a DRAM (Dynamic Random Access Memory) is provided in an exclusive well for memory cell and the memory cell is electrically isolated from a well for peripheral circuit.